![verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit8”---Sequential circuit8](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit8”---Sequential circuit8)
1、题目2、分析观察p发现p部分和a一样并且当clock为1时paclock为0时p保持不变q只在clock的下降沿发生变化观察得到q是p的时钟下降沿采样3、代码module top_module ( input clock, input a, output p, output q ); always (negedge clock) begin q p; end assign p clock ? a :p; endmodule4、结果 verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit8”---Sequential circuit8
1、题目2、分析观察p发现p部分和a一样并且当clock为1时paclock为0时p保持不变q只在clock的下降沿发生变化观察得到q是p的时钟下降沿采样3、代码module top_module ( input clock, input a, output p, output q ); always (negedge clock) begin q p; end assign p clock ? a :p; endmodule4、结果