1、题目Consider the FSM described by the state diagram shown below:This FSM acts as an arbiter circuit, which controls access to some type of resource by three requesting devices. Each device makes its request for the resource by setting a signalr[i] 1, wherer[i]is eitherr[1],r[2], orr[3]. Each r[i] is an input signal to the FSM, and represents one of the three devices. The FSM stays in stateAas long as there are no requests. When one or more request occurs, then the FSM decides which device receives a grant to use the resource and changes to a state that sets that device’sg[i]signal to 1. Eachg[i]is an output from the FSM. There is a priority system, in that device 1 has a higher priority than device 2, and device 3 has the lowest priority. Hence, for example, device 3 will only receive a grant if it is the only device making a request when the FSM is in stateA. Once a device,i, is given a grant by the FSM, that device continues to receive the grant as long as its request,r[i] 1.Write complete Verilog code that represents this FSM. Use separate always blocks for the state table and the state flip-flops, as done in lectures. Describe the FSM outputs,g[i], using either continuous assignment statement(s) or an always block (at your discretion). Assign any state codes that you wish to use.2、代码module top_module ( input clk, input resetn, // active-low synchronous reset input [3:1] r, // request output [3:1] g // grant ); parameter A4b0001,B4B0010,C4B0100,D4b1000; reg [4:1]state,next_state; always(posedge clk) if(!resetn) stateA; else statenext_state; assign next_state[1]state[1](~r[1](~r[2](~r[3])))||state[2](~r[1])||state[3](~r[2])||state[4](~r[3]); assign next_state[2]state[1]r[1]||state[2]r[1]; assign next_state[3]state[1](~r[1]r[2])||state[3]r[2]; assign next_state[4]state[1](~r[1](~r[2]r[3]))||state[4]r[3]; assign g[3:1]state[4:2]; endmodule 或者 module top_module ( input clk, input resetn, // active-low synchronous reset input [3:1] r, // request output [3:1] g // grant ); parameter A4b0001,B4B0010,C4B0100,D4b1000; reg [4:1]state,next_state; always(posedge clk) if(!resetn) stateA; else statenext_state; always(*)begin next_state A; // 新增默认赋值兜底所有未覆盖分支 case(state) A:begin if(r3b000) next_stateA; else if(r3b100) next_stateD; else if(r[2:1]2b10) next_stateC; else if(r[1]1b1) next_stateB; end B:begin if(r[1]1b1) next_stateB; else next_stateA; end C:begin if(r[2]1b1) next_stateC; else next_stateA; end D:begin if(r[3]1b1) next_stateD; else next_stateA; end default:next_stateA; endcase end assign g[3:1]state[4:2]; endmodule