verilog HDLBits刷题[Finite State Machines]“Exams/2014 q3bfsm”---Q3b:FSM

1、题目Given the state-assigned table shown below, implement the finite-state machine. Reset should reset the FSM to state 000.Present statey[2:0]Next state Y[2:0]Output zx0x1000000001000100110000100100010011001010110001110012、代码module top_module ( input clk, input reset, // Synchronous reset input x, output z ); parameter A3b000,B3b001,C3b010,D3b011,E3B100; reg [2:0]state,next_state; always(posedge clk)begin if(reset) stateA; else statenext_state; end always(*)begin case(state) A: next_statex?B:A; B:next_statex?E:B; C:next_statex?B:C; D:next_statex?C:B; E:next_statex?E:D; default:next_stateA; endcase end assign z(stateD||stateE); endmodule