本文将以 TC333 芯片为基础讲解英飞凌 TC3xx 系列芯片 ADC 模块的使用与配置方法。相关内容将参考以下手册配置重点部分会注明信息出处《AURIX™ TC3xx User Manual Part-1/2》TC3xx 系列芯片通用配置流程、《AURIX™ TC33x_TC32x User Manual》TC33x 系列芯片特殊配置流程、《AURIX™ TC33x_TC32x Errata Sheet》及《AURIX™ TC33x_TC32x Data Sheet》。增强型多功能模数转换器EVADCTC333 芯片集成 1 个 EVADC 模块增强型 ADC 模块目的可独立配置转换规则支持并行 ADC 转换任务。注意每个通道组通道数固定不同通道组之间的通道资源隔离。ADC通道使能配置G0第 0 个通道组G1第 1 个通道组G8第 8 个通道组EVADC_G0CHCTR0.U 0x00000000;/* 启用 group0组的通道0 即 group0_0 */EVADC_G1CHCTR0.U 0x00000000;/* 启用 group1组的通道0 即 group1_0 */EVADC_G8CHCTR1.U 0x00010000;/* 启用 group8组的通道1 即 group8_1 */ADC通道的转换规则队列配置G0QINR0通道组 0 的 Que0 的输入寄存器G1QINR0通道组 1 的 Que0 的输入寄存器G8QINR0通道组 8 的 Que0 的输入寄存器leg:EVADC_G8QCTRL0.U 0x0081AF00;/* que Ctrl reg 设置SWTRIG1触发软件转换*/EVADC_G8QMR0.U 0x00000405; /* que Mode reg 设置TREV0单次转换不自动重复、TRIG0软件触发*/EVADC_G8QINR0.U 0x000000A1; /* G8_1 */EVADC_G8QINR0.U 0x000000A2; /* G8_2 */EVADC_G8QINR0.U 0x000000A3; /* G8_3 */EVADC_G8QINR0.U 0x000000A4; /* G8_4 */EVADC_G8QINR0.U 0x000000A5; /* G8_5 */EVADC_G8QINR0.U 0x000000A7; /* G8_7 */EVADC_G8QINR0.U 0x000000AD; /* G8_13 */EVADC_G8QINR0.U 0x000000AF; /* G0_15 */下面是T333手册中关于GxQINRx寄存器的介绍代码是基于TC333芯片的详细ADC配置代码介绍注释void EVAdc_Init(void) { EVADC_GLOBCFG.U 0x80008001; /* clock fADCI 100MHz*/ EVADC_G0ANCFG.U 0x00300004; /* G0 Collection accuracy */ EVADC_G1ANCFG.U 0x00300004; /* G1 Collection accuracy */ EVADC_G8ANCFG.U 0x00300004; /* G8 Collection accuracy */ EVADC_G0ICLASS0.U 0x00000001; /* Que0 interruption */ EVADC_G1ICLASS0.U 0x00000001; /* Que1 interruption */ EVADC_G8ICLASS0.U 0x00000001; /* Que8 interruption */ EVADC_G0ARBCFG.U 0x00000003; /* Que0 priority */ EVADC_G1ARBCFG.U 0x00000003; /* Que1 priority */ EVADC_G8ARBCFG.U 0x00000003; /* Que8 priority */ EVADC_G0ARBPR.U 0x0700000B; /*G0 Arbitration Mode Rules*/ EVADC_G1ARBPR.U 0x0700000B; /*G1 Arbitration Mode Rules*/ EVADC_G8ARBPR.U 0x0700000B; /*G8 Arbitration Mode Rules*/ EVADC_G0CHCTR0.U 0x00000000; /* en group 0 channels */ EVADC_G0CHCTR7.U 0x00070000; EVADC_G1CHCTR0.U 0x00000000; /* en group 1 channels */ EVADC_G1CHCTR7.U 0x00070000; EVADC_G8CHCTR1.U 0x00010000; /* en group 8 channels */ EVADC_G8CHCTR2.U 0x00020000; EVADC_G8CHCTR3.U 0x00030000; EVADC_G8CHCTR4.U 0x00040000; EVADC_G8CHCTR5.U 0x00050000; EVADC_G8CHCTR7.U 0x00070000; EVADC_G8CHCTR7.U 0x000D0000; EVADC_G8CHCTR7.U 0x000F0000; EVADC_G0QCTRL0.U 0x0081AF00; /* que0 Ctrl reg */ EVADC_G0QMR0.U 0x00000405; /* que0 Mode reg */ EVADC_G0QINR0.U 0x000000A0; /* G0_0 */ EVADC_G0QINR0.U 0x000000A7; /* G0_7 */ EVADC_G1QCTRL0.U 0x0081AF00; EVADC_G1QMR0.U 0x00000405; EVADC_G1QINR0.U 0x000000A0; /* G1_0 */ EVADC_G1QINR0.U 0x000000A7; /* G1_7 */ EVADC_G8QCTRL0.U 0x0081AF00; EVADC_G8QMR0.U 0x00000405; EVADC_G8QINR0.U 0x000000A1; /* G8_1 */ EVADC_G8QINR0.U 0x000000A2; /* G8_2 */ EVADC_G8QINR0.U 0x000000A3; /* G8_3 */ EVADC_G8QINR0.U 0x000000A4; /* G8_4 */ EVADC_G8QINR0.U 0x000000A5; /* G8_5 */ EVADC_G8QINR0.U 0x000000A7; /* G8_7 */ EVADC_G8QINR0.U 0x000000AD; /* G8_13 */ EVADC_G8QINR0.U 0x000000AF; /* G0_15 */ EVADC_G0QCTRL1.U 0x00000000;/* no use */ EVADC_G0QMR1.U 0x00000405; EVADC_G0QINR1.U 0x00000020; EVADC_G0QINR1.U 0x00000022; EVADC_G0QINR1.U 0x00000023; EVADC_G0QINR1.U 0x00000025; EVADC_G0QINR1.U 0x00000022; EVADC_G1QCTRL1.U 0x00000000;/* no use */ EVADC_G1QMR1.U 0x00000405; EVADC_G1QINR1.U 0x00000020; EVADC_G1QINR1.U 0x00000021; EVADC_G1QINR1.U 0x00000023; EVADC_G1QINR1.U 0x00000024; EVADC_G1QINR1.U 0x00000025; EVADC_G1QINR1.U 0x00000021; EVADC_G8QCTRL1.U 0x00000000;/* no use */ EVADC_G8QMR1.U 0x00000405; EVADC_G8QINR1.U 0x00000020; EVADC_G8QINR1.U 0x00000022; EVADC_G8QINR1.U 0x00000024; EVADC_G8QINR1.U 0x00000025; EVADC_G8QINR1.U 0x00000022; }