verilog HDLBits刷题[Karnaugh Map to Circuit]---K-map implemented with a multiplexer
题目For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must useaandbas the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.You are implementing just the portion labelledtop_module, such that the entire circuit (including the 4-to-1 mux) implements the K-map.固定ab00观察不同cd对应的f输出为mux_in[0]答案module top_module ( input c, input d, output [3:0] mux_in ); always (*)begin case({c,d}) 2b00:mux_in4b0100; 2b01:mux_in4b0001; 2b11:mux_in4b1001; 2b10:mux_in4b0101; endcase end endmodule波形